1. Field of the Disclosure
The following relates generally to circuit design and more specifically, but not exclusively, to routing a wire in two-dimensions (2-D) or three-dimension (3-D) based on time-variant temperature characteristics.
2. Description of Related Art
Algorithms for routing wires, sometimes referred to as traces or electrical paths, on or within printed circuit boards (PCBs), integrated circuits (ICs), or other structures attempt to find the routes that best meet the routing requirements for the wires. In general, routing requirements dictate that the wires should be as short as possible. In this way, power consumption and signal propagation delay associated with the transmission of a signal over a wire is minimized at least to some degree. Moreover, the use of shorter wires enables more wires to be routed within a given area, thereby improving circuit density.
In some applications, routing requirements specify that the lengths of multiple wires be equal or nearly equal. For example, in timing critical applications that employ clock trees or that employ parallel wires (e.g., for busses or differential signals), the use of equal wire lengths makes it easier to match the signal propagation characteristics of the wires. Consequently, a signal or signals from one or more data sources may reach multiple data sinks via different wires at approximately the same time, thereby maintaining a desired timing relationship between the signals at the data sinks. In other words, matched wires are employed to keep the relative timing skew of signals transmitted over different wires to a minimum.
Other techniques have been proposed to reduce timing skew. For example, some systems use buffers to control the delay along a wire and thereby reduce timing skew. Other system insert crosslinks into the wiring structure to reduce timing skew.
In practice, however, the above techniques may not sufficiently reduce timing skew or may have certain drawbacks. For example, various operating conditions and environmental factors may affect the propagation delay of a signal through a wire. Thus, it may be difficult to match the signal propagation characteristics of different wires, even if the wire lengths are matched. Also, active techniques such as buffer insertion, can lead to a significant increase in power consumption. In addition, as crosslink link insertion can increase the wire length, an increase in power consumption may be seen in these scenarios as well. In view of the above, a need exists for improved circuit design techniques.
The parent application, noted above, was directed, at least in part, to providing various temperature-based circuit wiring techniques. The present application is directed, at least in part, to additional or alternative temperature-based circuit wiring techniques.